US 11,942,165 B2
Architecture and method for NAND memory programming
Weijun Wan, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Apr. 20, 2022, as Appl. No. 17/725,144.
Application 17/725,144 is a continuation in part of application No. 17/149,080, filed on Jan. 14, 2021, granted, now 11,328,781.
Application 17/149,080 is a continuation of application No. PCT/CN2020/117315, filed on Sep. 24, 2020.
Prior Publication US 2022/0246224 A1, Aug. 4, 2022
Int. Cl. G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
memory cells; and
a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells,
wherein the first latch circuit is configured to store verification data during a verification operation,
the second latch circuit is configured to store failure pattern data during the verification operation,
the third latch circuit is configured to store program data,
the verification data comprises inhibit information and inverted inhibit information, and
the inverted inhibit information is configured to indicate unverified states of the memory cells that include a first state and remaining states subsequent to the first state.