US 11,942,161 B2
Secure memory device and erase method thereof
Tse-Yen Liu, Taipei (TW)
Assigned to NUVOTON TECHNOLOGY CORPORATION, Hsinchu Science Park (TW)
Filed by Nuvoton Technology Corporation, Hsinchu Science Park (TW)
Filed on Dec. 23, 2021, as Appl. No. 17/560,488.
Claims priority of application No. 202111414402.2 (CN), filed on Nov. 25, 2021.
Prior Publication US 2023/0162800 A1, May 25, 2023
Int. Cl. G11C 16/16 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01); H03K 19/20 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/102 (2013.01); G11C 16/32 (2013.01); H03K 19/20 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a main memory, storing a first security control signal;
a first sub-memory, wherein in response to the first sub-memory being erased, the first sub-memory outputs an enabled first erase completion signal, wherein the first sub-memory operates in a locked state according to the first security control signal; and
a controller, receiving an erase signal to erase the main memory, wherein the controller performs an erase operation on the main memory according to the erase signal and the first erase completion signal.