US 11,942,159 B2
Selective management of erase operations in memory devices that enable suspend commands
Chulbum Kim, San Jose, CA (US); Brian Kwon, Fremont, CA (US); Erwin E. Yu, San Jose, CA (US); Kitae Park, Cupertino, CA (US); and Taehyun Kim, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 2, 2022, as Appl. No. 17/591,510.
Claims priority of provisional application 63/237,282, filed on Aug. 26, 2021.
Prior Publication US 2023/0063656 A1, Mar. 2, 2023
Int. Cl. G11C 16/14 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/22 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/14 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/225 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising memory cells; and
control logic operatively coupled with the memory array, the control logic to perform operations comprising:
initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array;
tracking a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse;
causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and
in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.