CPC G11C 16/14 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/225 (2013.01); G11C 16/32 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory array comprising memory cells; and
control logic operatively coupled with the memory array, the control logic to perform operations comprising:
initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array;
tracking a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse;
causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and
in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.
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