US 11,942,158 B2
Semiconductor memory device
Naoya Tokiwa, Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Nov. 29, 2022, as Appl. No. 18/071,470.
Application 18/071,470 is a continuation of application No. 17/181,998, filed on Feb. 22, 2021, granted, now 11,551,760.
Application 17/181,998 is a continuation of application No. 16/802,446, filed on Feb. 26, 2020, granted, now 10,950,307, issued on Mar. 16, 2021.
Claims priority of application No. 2019-083092 (JP), filed on Apr. 24, 2019.
Prior Publication US 2023/0118624 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 7/06 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 7/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device including:
a memory string;
a sense amplifier connected to the memory string through a bit line;
a signal line connected to the sense amplifier;
a first latch including a first input and a first output, the first input of the first latch connected to the signal line;
a second latch including a second input and a second output, the second input of the second latch connected to the first output of the first latch; and
a third latch including a third input and a third output, the third input of the third latch connected to the second output of the second latch, the third output of the third latch connected to the signal line.