US 11,942,157 B2
Variable bit line bias for nonvolatile memory
Jiacen Guo, Sunnyvale, CA (US); Xiang Yang, Santa Clara, CA (US); and Xiaochen Zhu, Milpitas, CA (US)
Assigned to SanDisk Technologies LLC, Austin, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Mar. 17, 2022, as Appl. No. 17/697,252.
Prior Publication US 2023/0298667 A1, Sep. 21, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/04 (2006.01); H10B 43/27 (2023.01)
CPC G11C 16/10 (2013.01) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/0483 (2013.01); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a word line coupled to a word line driver circuit;
a plurality of bit lines;
a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines; and
a control circuit coupled to the word line and the bit lines, the control circuit configured to program the memory cells by:
causing the word line driver to apply a program pulse to the word line; and
biasing each bit line to a corresponding bit line voltage that decreases linearly with increasing distance between the word line driver and the corresponding bit line.