CPC G11C 16/10 (2013.01) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/0483 (2013.01); H10B 43/27 (2023.02)] | 20 Claims |
1. An apparatus comprising:
a word line coupled to a word line driver circuit;
a plurality of bit lines;
a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines; and
a control circuit coupled to the word line and the bit lines, the control circuit configured to program the memory cells by:
causing the word line driver to apply a program pulse to the word line; and
biasing each bit line to a corresponding bit line voltage that decreases linearly with increasing distance between the word line driver and the corresponding bit line.
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