CPC G11C 13/004 (2013.01) [G11C 2013/0054 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory array of memory cells, each memory cell being a resistive memory cell;
a sense circuit coupled to the memory array; and
an access line biasing circuit to control a clamp current for the memory cell of the memory array, with the clamp current being provided by the access line biasing circuit to the memory cell opposite the coupling of the sense circuit to the memory array.
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