US 11,942,151 B2
Current references for memory cells
Ferdinando Bedeschi, Biassono (IT); Pierguido Garofalo, San Donato (IT); Umberto Di Vincenzo, Capriate San Gervasio (IT); and Claudia Palattella, Cologno Monzese (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 14, 2022, as Appl. No. 17/720,957.
Prior Publication US 2023/0335191 A1, Oct. 19, 2023
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 2013/0054 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array of memory cells, each memory cell being a resistive memory cell;
a sense circuit coupled to the memory array; and
an access line biasing circuit to control a clamp current for the memory cell of the memory array, with the clamp current being provided by the access line biasing circuit to the memory cell opposite the coupling of the sense circuit to the memory array.