US 11,942,145 B2
Static random access memory layout
Chih-Chuan Yang, Hsinchu (TW); Jui-Wen Chang, Hsinchu (TW); Feng-Ming Chang, Zhongli (TW); Kian-Long Lim, Hsinchu (TW); Kuo-Hsiu Hsu, Zhongli (TW); Lien Jung Hung, Taipei (TW); and Ping-Wei Wang, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 6, 2022, as Appl. No. 17/662,364.
Claims priority of provisional application 63/222,580, filed on Jul. 16, 2021.
Prior Publication US 2023/0012621 A1, Jan. 19, 2023
Int. Cl. G11C 5/06 (2006.01); G11C 11/417 (2006.01); H01L 29/423 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/417 (2013.01) [H01L 29/42392 (2013.01); H10B 10/125 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for memory cell placement, comprising:
placing a memory cell region in a layout area;
placing, in the layout area, a well pick-up region and a first power supply routing region along a first side of the memory cell region;
placing, in the layout area, a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, wherein the second side is on an opposite side to that of the first side; and
placing, in the layout area, a device region along the second side of the memory cell region, wherein the bitline jumper routing region is between the second power supply routing region and the device region, and wherein placing the memory cell region, the well pick-up region, the first power supply routing region, the second power supply routing region, the bitline jumper routing region, and the device region are performed by one or more processors.