US 11,942,142 B2
Memory subword driver circuits with common transistors at word lines
Shinichi Miyatake, Kanagawa (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 12, 2022, as Appl. No. 17/931,457.
Application 17/931,457 is a continuation of application No. 17/006,722, filed on Aug. 28, 2020, granted, now 11,488,655.
Prior Publication US 2023/0005519 A1, Jan. 5, 2023
Int. Cl. G11C 8/08 (2006.01); G11C 8/14 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4085 (2013.01) [G11C 8/08 (2013.01); G11C 8/14 (2013.01); G11C 11/4074 (2013.01); G11C 11/408 (2013.01); G11C 11/4087 (2013.01); G11C 11/4094 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first main word line;
a second main word line;
a third main word line;
a first subword driver coupled to a first common transistor and the first main word line;
a second subword driver coupled to the first common transistor and the second main word line;
a third subword driver coupled to a second common transistor and the first main word line; and
a fourth subword driver coupled to the second common transistor and the third main word line, wherein
the apparatus further comprises:
a third common transistor;
a fifth subword driver; and
a sixth subword driver, wherein at least the fifth subword driver and the six subword driver are coupled to the third common transistor,
the apparatus further comprises:
a fourth common transistor;
a seventh subword driver; and
an eighth subword driver, wherein the seventh subword driver and the eighth subword driver are coupled to the fourth common transistor, and
the fifth and seventh subword drivers are coupled to the first main word line, the sixth subword driver is coupled to the second main word line, and the eighth subword driver is coupled to the third main word line.