US 11,942,138 B2
Memory system including semiconductor memory device and operation method thereof
Woongrae Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Apr. 15, 2022, as Appl. No. 17/721,708.
Claims priority of application No. 10-2021-0157713 (KR), filed on Nov. 16, 2021.
Prior Publication US 2023/0154518 A1, May 18, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/40611 (2013.01) [G11C 11/4085 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory device suitable for:
providing row-hammer data to set refresh rates for adjacent word lines of a target word line, and
performing a target refresh operation on one or more word lines corresponding to a first row-hammer address according to a first target refresh command; and
a memory controller suitable for:
generating a plurality of sampling addresses by sampling an active address,
generating a plurality of counting values corresponding to the plurality of sampling addresses by comparing the plurality of sampling addresses with the active address and incrementing a counting value of the plurality of counting values for a match in the comparing of the plurality of sampling addresses with the active address,
calculating, when there is the match between the plurality of sampling addresses and the active address, a plurality of adjacent addresses corresponding to and incrementally changed from the plurality of sampling addresses based on the plurality of counting values and the row-hammer data, and
providing the plurality of adjacent addresses as the first row-hammer address with the first target refresh command.