| CPC G11C 11/406 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06N 7/01 (2023.01)] | 20 Claims |
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1. A memory controller configured to control a semiconductor memory device, the memory controller comprising:
an access pattern profiler configured to generate a first access pattern profile based on a first row access pattern associated with a first access on at least a second portion of a plurality of memory cell rows of the semiconductor memory device during a first reference time interval posterior to a first refresh interval during which at least a first portion of the plurality of memory cell rows are refreshed;
a row hammer prediction neural network configured to:
perform machine learning based on learning data,
predict a first probability of occurrence of a row hammer in which at least one of the plurality of memory cell rows is intensively accessed by the first row access pattern, based on the first access pattern profile, and
in response to the first probability being equal to or greater than a reference value, generate a hammer address associated with the row hammer, an outcast row list, and an alert signal indicating that the row hammer occurs, the outcast row list being associated with outcast memory cell rows from among the plurality of memory cell rows, which are excluded from a hammer refresh operation that is performed in the semiconductor memory device in response to the first row access pattern; and
a memory interface configured to transmit the hammer address, the outcast row list and the alert signal to the semiconductor memory device.
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