CPC G11C 11/4023 (2013.01) [G11C 11/409 (2013.01); H01L 29/22 (2013.01); H01L 29/7827 (2013.01); H10B 99/00 (2023.02)] | 20 Claims |
1. A method comprising:
applying a first voltage to an access line of a volatile memory device, the access line controlling a first transistor and a second transistor of a memory cell of the volatile memory device during an operation of storing information in a memory element of the memory cell, the memory element directly coupled to a channel region of the second transistor, the first and second transistors having different threshold voltages, the volatile memory device including a first data line coupled to the first transistor, a second data line coupled to the first transistor, and a third data line coupled to the second transistor;
placing each of the first and second data lines in a float condition during the operation; and
applying a second voltage to the third data line during the operation.
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