US 11,942,136 B2
Memory device having shared read/write access line for 2-transistor vertical memory cell
Karthik Sarpatwari, Boise, ID (US); Kamal M. Karda, Boise, ID (US); and Durai Vishak Nirmal Ramaswamy, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 15, 2022, as Appl. No. 17/887,903.
Application 17/887,903 is a division of application No. 16/725,643, filed on Dec. 23, 2019, granted, now 11,417,381.
Claims priority of provisional application 62/785,136, filed on Dec. 26, 2018.
Prior Publication US 2022/0392511 A1, Dec. 8, 2022
Int. Cl. G11C 11/402 (2006.01); G11C 11/409 (2006.01); H01L 29/22 (2006.01); H01L 29/78 (2006.01); H10B 99/00 (2023.01)
CPC G11C 11/4023 (2013.01) [G11C 11/409 (2013.01); H01L 29/22 (2013.01); H01L 29/7827 (2013.01); H10B 99/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
applying a first voltage to an access line of a volatile memory device, the access line controlling a first transistor and a second transistor of a memory cell of the volatile memory device during an operation of storing information in a memory element of the memory cell, the memory element directly coupled to a channel region of the second transistor, the first and second transistors having different threshold voltages, the volatile memory device including a first data line coupled to the first transistor, a second data line coupled to the first transistor, and a third data line coupled to the second transistor;
placing each of the first and second data lines in a float condition during the operation; and
applying a second voltage to the third data line during the operation.