US 11,942,134 B2
Memory circuit and write method
Huan-Sheng Wei, Hsinchu (TW); Tzer-Min Shen, Hsinchu (TW); and Zhiqiang Wu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 18, 2022, as Appl. No. 18/056,807.
Application 18/056,807 is a continuation of application No. 17/198,790, filed on Mar. 11, 2021, granted, now 11,508,427.
Claims priority of provisional application 63/031,204, filed on May 28, 2020.
Prior Publication US 2023/0083548 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/22 (2006.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01)
CPC G11C 11/2275 (2013.01) [G11C 11/223 (2013.01); G11C 11/2273 (2013.01); H10B 51/30 (2023.02); H10B 51/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a memory array comprising a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
an n-type channel layer comprising a metal oxide material; and
a gate structure overlying and adjacent to the n-type channel layer, the gate structure comprising a conductive layer overlying a ferroelectric layer,
wherein
the memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations,
the gate voltage has a positive polarity and a first magnitude in the first write operation, and
the gate voltage has a negative polarity and a second magnitude greater than the first magnitude in the second write operation.