CPC G11C 11/1673 (2013.01) [G06F 9/4401 (2013.01); G06F 21/575 (2013.01); G11C 5/148 (2013.01); G11C 11/4023 (2013.01); G11C 11/404 (2013.01); H10B 12/30 (2023.02); G11C 2211/4016 (2013.01)] | 16 Claims |
1. A semiconductor device comprising:
a processor; and
a memory circuit comprising a first memory cell array and a second memory cell array,
wherein the first memory cell array comprises a plurality of first memory cells arranged in a matrix,
wherein each of the plurality of first memory cells comprises a first transistor and a first capacitor electrically connected to the first transistor,
wherein the second memory cell array comprises a plurality of second memory cells arranged in a matrix,
wherein each of the plurality of second memory cells comprises a second transistor and a second capacitor electrically connected to the second transistor,
wherein the first memory cell array is configured to store data for executing a start-up routine of the processor while power supply to the semiconductor device is stopped, and
wherein the second memory cell array is configured to be used as a work area for arithmetic operation when the processor is in normal operation.
|