US 11,942,132 B2
Semiconductor device, electronic component, and electronic device
Yoshiyuki Kurokawa, Sagamihara (JP); and Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 28, 2022, as Appl. No. 18/089,703.
Application 18/089,703 is a continuation of application No. 17/382,692, filed on Jul. 22, 2021, granted, now 11,545,203.
Application 17/382,692 is a continuation of application No. 16/617,919, granted, now 11,074,953, issued on Jul. 27, 2021, previously published as PCT/IB2018/054072, filed on Jun. 7, 2018.
Claims priority of application No. 2017-118247 (JP), filed on Jun. 16, 2017.
Prior Publication US 2023/0139527 A1, May 4, 2023
Int. Cl. G11C 11/16 (2006.01); G06F 9/4401 (2018.01); G06F 21/57 (2013.01); G11C 5/14 (2006.01); G11C 11/402 (2006.01); G11C 11/404 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/1673 (2013.01) [G06F 9/4401 (2013.01); G06F 21/575 (2013.01); G11C 5/148 (2013.01); G11C 11/4023 (2013.01); G11C 11/404 (2013.01); H10B 12/30 (2023.02); G11C 2211/4016 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a processor; and
a memory circuit comprising a first memory cell array and a second memory cell array,
wherein the first memory cell array comprises a plurality of first memory cells arranged in a matrix,
wherein each of the plurality of first memory cells comprises a first transistor and a first capacitor electrically connected to the first transistor,
wherein the second memory cell array comprises a plurality of second memory cells arranged in a matrix,
wherein each of the plurality of second memory cells comprises a second transistor and a second capacitor electrically connected to the second transistor,
wherein the first memory cell array is configured to store data for executing a start-up routine of the processor while power supply to the semiconductor device is stopped, and
wherein the second memory cell array is configured to be used as a work area for arithmetic operation when the processor is in normal operation.