CPC G11C 11/1673 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01); G11C 11/54 (2013.01)] | 20 Claims |
1. A processing apparatus comprising:
a bit-cell array comprising at least one bit-cell line including a plurality of bit-cells electrically connected to each other in series,
wherein each of the plurality of bit-cells comprises:
a first magnetic resistor that is configured to store a first resistance value based on a movement of a location of a magnetic domain-wall;
a second magnetic resistor that is configured to store a second resistance value, wherein the second resistance value is equal to or less than the first resistance value;
a first switching element configured to switch an electrical signal applied to the first magnetic resistor; and
a second switching element configured to switch an electrical signal applied to the second magnetic resistor.
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