US 11,942,130 B2
Bottom-pinned spin-orbit torque magnetic random access memory and method of manufacturing the same
Jian-Jhong Chen, Tainan (TW); Yi-Ting Wu, Tainan (TW); Jen-Yu Wang, Tainan (TW); Cheng-Tung Huang, Kaohsiung (TW); Po-Chun Yang, Tainan (TW); and Yung-Ching Hsieh, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Mar. 23, 2022, as Appl. No. 17/701,703.
Claims priority of application No. 202210197858.6 (CN), filed on Mar. 2, 2022.
Prior Publication US 2023/0282260 A1, Sep. 7, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC G11C 11/161 (2013.01) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A bottom-pinned spin-orbit torque magnetic random access memory, comprising:
a substrate;
a bottom electrode layer on said substrate;
a magnetic tunnel junction on said bottom electrode layer;
a spin-orbit torque layer on said magnetic tunnel junction;
a capping layer on said spin-orbit torque layer, wherein said capping layer, said spin-orbit torque layer, said magnetic tunnel junction and said bottom electrode layer constitute a memory unit;
an injection layer on said capping layer, wherein said injection layer is divided into a first part and a second part, and said first part and said second part are connected respectively with two ends of said capping layer; and
an insulating layer between said first part and said second part of said injection layer, wherein a top surface of said insulating layer is flush with top surfaces of said first part and said second part of said injection layer.