US 11,942,058 B2
Pulse output circuit, shift register, and display device
Seiko Amano, Kanagawa (JP); and Hiroyuki Miyake, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Oct. 7, 2022, as Appl. No. 17/961,778.
Application 17/961,778 is a continuation of application No. 17/458,656, filed on Aug. 27, 2021, granted, now 11,468,860.
Application 17/458,656 is a continuation of application No. 17/073,634, filed on Oct. 19, 2020, granted, now 11,107,432, issued on Aug. 31, 2021.
Application 17/073,634 is a continuation of application No. 15/393,389, filed on Dec. 29, 2016, granted, now 10,818,256, issued on Oct. 27, 2020.
Application 15/393,389 is a continuation of application No. 14/831,939, filed on Aug. 21, 2015, granted, now 9,543,039, issued on Jan. 10, 2017.
Application 14/831,939 is a continuation of application No. 13/111,064, filed on May 19, 2011, granted, now 9,117,537, issued on Aug. 25, 2015.
Claims priority of application No. 2010-117615 (JP), filed on May 21, 2010.
Prior Publication US 2023/0107990 A1, Apr. 6, 2023
Int. Cl. G09G 3/36 (2006.01); G06F 1/3234 (2019.01); G06F 3/038 (2013.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H01L 27/12 (2006.01); G09G 5/00 (2006.01)
CPC G09G 3/3677 (2013.01) [G06F 1/3265 (2013.01); G06F 3/038 (2013.01); G09G 3/3266 (2013.01); G11C 19/28 (2013.01); H01L 27/124 (2013.01); G09G 5/008 (2013.01); G09G 2300/0809 (2013.01); G09G 2300/0871 (2013.01); G09G 2310/0205 (2013.01); G09G 2310/0248 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/021 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first pulse output circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the fourth wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the fourth wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a sixth wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a seventh wiring,
wherein a gate of the first transistor is electrically connected to a gate of the third transistor,
wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the sixth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,
wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the seventh transistor,
wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the eighth transistor,
wherein a gate of the fifth transistor is electrically connected to an eighth wiring which is configured to supply a start pulse, and
wherein a gate of the eighth transistor is directly connected to the eighth wiring.