| CPC G06N 20/10 (2019.01) [G06F 9/30134 (2013.01)] | 15 Claims |
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1. An electronic apparatus comprising:
a memory comprising circuitry and configured to store input data and a plurality of second kernel data obtained from first kernel data such that each of the plurality of second kernel data comprises a different first kernel element from among a plurality of first kernel elements in the first kernel data; and
a processor comprising circuitry and configured to perform a convolution operation on each of the plurality of second kernel data with the input data, shuffle the performed convolution operation and obtain upscaled data in which at least a portion of the input data is upscaled by the first kernel data based on the plurality of shuffled operation results,
wherein the processor is configured to divide the plurality of first kernel elements in the first kernel data into a plurality of groups, add zeros to each of the plurality of groups based on at least one first kernel element included in each of the plurality of groups so that each of the plurality of groups includes a predetermined number of second kernel elements, and obtain the plurality of second kernel data based on the plurality of groups having the zeros,
wherein a size of each of the plurality of second kernel data is determined based on a size of the first kernel data, and
wherein the processor comprises:
a convolution array comprising circuitry and configured to perform the convolution operation on each of the plurality of second kernel data with the input data by performing a parallel operation through a plurality of processing elements,
a line memory comprising circuitry and configured to store the upscaled data, and
a shuffler comprising circuitry and positioned between the convolution array and the line memory and configured to shuffle a plurality of operation results output from the convolution array and output the plurality of shuffled operation results to the line memory.
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