US 11,941,409 B2
Methods, systems, and apparatuses for a multiprocessor boot flow for a faster boot process
Subrata Banik, Bangalore (IN); Asad Azam, El Dorado Hills, CA (US); Jenny M. Pelner, Phoenix, AZ (US); Vincent Zimmer, Issaquah, WA (US); and Rajaram Regupathy, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 27, 2020, as Appl. No. 16/914,331.
Prior Publication US 2021/0326142 A1, Oct. 21, 2021
Int. Cl. G06F 9/44 (2018.01); G06F 9/4401 (2018.01)
CPC G06F 9/4403 (2013.01) [G06F 2212/60 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A hardware processor comprising:
a processor core;
a cache coupled to the processor core; and
a controller circuit to initialize a portion of the cache as memory for hardware initialization code usage before beginning execution of the hardware initialization code after a power on of the hardware processor, and provide an indication to the hardware initialization code of a start and a limit of the portion of the cache usable by the hardware initialization code.