US 11,941,407 B2
Pipeline architecture for bitwise multiplier-accumulator (MAC)
Avidan Akerib, Tel Aviv (IL)
Assigned to GSI Technology Inc., Sunnyvale, CA (US)
Filed by GSI Technology Inc., Sunnyvale, CA (US)
Filed on Apr. 5, 2020, as Appl. No. 16/840,393.
Claims priority of provisional application 62/850,033, filed on May 20, 2019.
Prior Publication US 2020/0371813 A1, Nov. 26, 2020
Int. Cl. G06F 9/38 (2018.01); G06F 7/544 (2006.01); G06F 9/30 (2018.01)
CPC G06F 9/3893 (2013.01) [G06F 7/5443 (2013.01); G06F 9/30014 (2013.01); G06F 9/30079 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method for accumulating a plurality N of multiplied M bit values, the method comprising:
for each pair of multiplicands A and B, each of M bits:
in M rows, each of M multiplication units, separately multiplying each bit of said multiplicand A with each bit of said multiplicand B and separately summing results from a previous row of said multiplication units;
in M rows of summing units following said M rows of multiplication units, separately summing results from a previous row of said summing units or said multiplication units, said rows summing output towards an accumulator formed as a column; and
in accumulator units of said accumulator, separately accumulating each bit of a result from the bit output of each row and passing carry values along the bits of said result from the LSB (least significant bit) to the MSB (most significant bit) of said result,
wherein said multiplication units, said summing units and said accumulator units are bit-line processors.