US 11,941,405 B2
Computational memory
William Martin Snelgrove, Toronto (CA); and Darrick John Wiebe, Toronto (CA)
Assigned to UNTETHER AI CORPORATION, Toronto (CA)
Filed by UNTETHER AI CORPORATION, Toronto (CA)
Filed on Jul. 27, 2023, as Appl. No. 18/227,092.
Application 18/227,092 is a continuation of application No. 18/126,574, filed on Mar. 27, 2023.
Application 18/126,574 is a continuation of application No. 16/975,097, granted, now 11,614,947, issued on Mar. 28, 2023, previously published as PCT/IB2018/056687, filed on Aug. 31, 2018.
Application 16/975,097 is a continuation in part of application No. 15/903,754, filed on Feb. 23, 2018, granted, now 11,514,294, issued on Nov. 29, 2022.
Claims priority of provisional application 62/648,074, filed on Mar. 26, 2018.
Prior Publication US 2023/0409338 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01)
CPC G06F 9/3887 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30101 (2013.01); G06F 12/0284 (2013.01); G06F 13/1668 (2013.01); G06F 13/287 (2013.01); G06F 13/4068 (2013.01); G06F 15/7821 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G06F 2212/1028 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a plurality of computational memory banks, each computational memory bank of the plurality of computational memory banks including an array of memory units and a plurality of processing elements connected to the array of memory units; and
a plurality of single instruction, multiple data (SIMD) controllers, each SIMD controller of the plurality of SIMD controllers being contained within at least one computational memory bank of the plurality of computational memory banks;
wherein each SIMD controller is to provide instructions to the at least one computational memory bank and control execution of the instructions by the at least one computational memory bank;
wherein each processing element of the plurality of processing elements includes registers and an arithmetic logic unit (ALU) to perform operations with the registers; and
wherein each processing element of the plurality of processing elements is to receive communicated state from registers of another processing element, the ALU to perform operations with the registers and the communicated state.