US 11,941,401 B1
Instruction fetch using a return prediction circuit
Pruthivi Vuyyuru, Santa Clara, CA (US); and Ian D. Kountanis, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 9, 2022, as Appl. No. 17/806,234.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3806 (2013.01) [G06F 9/30134 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor circuit including:
a return address stack circuit;
a return prediction circuit configured to store, for previously accessed return addresses, corresponding fetch parameters for next fetch addresses; and
a fetch control circuit configured to:
in response to an initial fetch of a call instruction:
push a return address onto the return address stack circuit; and
use the return address to determine whether a corresponding entry currently exists in the return prediction circuit; and
in response to an initial fetch of a return instruction that corresponds to the call instruction:
in response to a determination that the corresponding entry does not currently exist in the return prediction circuit, generate the corresponding entry for the return address based on particular fetch parameters determined when the return instruction is performed; and
in response to a subsequent fetch of the call instruction, push the return address onto the return address stack circuit; and
in response to a subsequent fetch of the return instruction that corresponds to the call instruction:
retrieve the return address from the return address stack circuit; and
create, using the return address and particular fetch parameters retrieved from the generated entry in the return prediction circuit, a next fetch request to retrieve instructions subsequent to the return instruction.