US 11,941,394 B2
Data element rearrangement, processors, methods, systems, and instructions
Christopher J. Hughes, Santa Clara, CA (US); and Jong Soo Park, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 9, 2019, as Appl. No. 16/708,399.
Application 16/708,399 is a continuation of application No. 14/865,696, filed on Sep. 25, 2015, granted, now 10,503,502.
Prior Publication US 2020/0117451 A1, Apr. 16, 2020
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30007 (2013.01) [G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30101 (2013.01); G06F 9/3016 (2013.01); G06F 9/30192 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a decode unit to decode an instruction, the instruction to indicate a source packed data operand that is to have a plurality of source data elements, to indicate a source packed indices operand that is to have a plurality of indices, and to have at least one field to specify a single destination packed data register, wherein each of the indices is to correspond to a different one of the source data elements in a same relative position, wherein each of the indices is to be represented in a lowest order subset of bits of a least significant byte of an associated data element; and
an execution unit coupled with the decode unit, the execution unit to perform the instruction to store a result packed data operand in the single destination packed data register, the result packed data operand to include a plurality of result data elements, each result data element to have a value of one of the source data elements whose corresponding index specifies a data element position of the result data element in the result packed data operand, wherein the execution unit is only to store result data elements in the single destination packed data register.