US 11,941,369 B1
Dual-domain combinational logic circuitry
Frederick A. Ware, Los Altos Hills, CA (US); and John Eric Linstadt, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Sep. 26, 2022, as Appl. No. 17/952,827.
Application 17/952,827 is a continuation of application No. 17/363,940, filed on Jun. 30, 2021, granted, now 11,481,192.
Application 17/363,940 is a continuation of application No. 16/503,346, filed on Jul. 3, 2019, granted, now 11,068,237, issued on Jul. 20, 2021.
Claims priority of provisional application 62/696,368, filed on Jul. 11, 2018.
Int. Cl. G06F 7/503 (2006.01); G06F 7/502 (2006.01); G06F 9/30 (2018.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01)
CPC G06F 7/503 (2013.01) [G06F 7/502 (2013.01); G06F 9/3001 (2013.01); G06F 9/30029 (2013.01); H03K 19/0021 (2013.01); H03K 19/018521 (2013.01)] 20 Claims
OG exemplary drawing
 
1. Signal driver circuitry within an integrated circuit device, the signal driver comprising:
first and second transistors having drain terminals coupled to one another, source terminals coupled respectively to upper and lower supply voltage nodes of a first voltage domain, and gate terminals coupled respectively to first and second control signal lines; and
third and fourth transistors having drain terminals coupled to one another and source terminals coupled respectively to upper and lower supply voltage nodes of a second voltage domain, the third transistor having a gate terminal coupled to one of the first and second control signal lines and the fourth transistor having a gate terminal coupled to the other of the first and second control signal lines.