CPC G06F 30/398 (2020.01) | 20 Claims |
1. A method comprising:
obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit, wherein the hierarchical macro comprises a parent macro and a plurality of child macros;
analyzing, by a design verification tool, a route between at least one child macro of the child macros and at least one pin of the hierarchical macro as defined in the files;
determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route;
calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics; and
adjusting, by the design verification tool, the design of the hierarchical macro to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule, wherein adjusting comprises:
generating a parent shape information file as one of the files based on determining that an antenna rule violation fix cannot be made at a parent level of the parent macro;
modifying the design of the hierarchical macro at a child level of the at least one child macro based on the parent shape information file;
updating a child shape information file of the files to include a modification of the design of the hierarchical macro; and
using the child shape information file after updating to run a subsequent parent antenna check.
|