US 11,941,336 B2
Three-dimensional FPGA with structure ASIC hardening capability
Kim Pin Tan, Jelutong (MY); and Hun Wah Cheah, Batu Mauang (MY)
Assigned to OPPSTAR TECHNOLOGY SDN BHD, Bayan Lepas (MY)
Filed by OPPSTAR TECHNOLOGY SDN BHD, Bayan Lepas (MY)
Filed on Nov. 10, 2021, as Appl. No. 17/523,525.
Prior Publication US 2023/0140876 A1, May 11, 2023
Int. Cl. G06F 30/347 (2020.01); G06F 115/06 (2020.01)
CPC G06F 30/347 (2020.01) [G06F 2115/06 (2020.01)] 19 Claims
OG exemplary drawing
 
1. A circuit device, comprising:
a first chip that includes a plurality of functional blocks, wherein the first chip lacks interconnections between the plurality of functional blocks; and
a second chip that includes:
routing circuitry that provides configurable signal communications between functional blocks of the first chip; and
configuration memory that controls the routing circuitry and that further controls operation of the plurality of functional blocks of the first chip.