US 11,941,335 B1
Providing concise data for analyzing checker completeness
Amit Verma, Uttar Pradesh (IN); Yumi Monma, Belo Horizonte (BR); David Spatafore, Maple Grove, MN (US); Suyash Kumar, Uttar Pradesh (IN); and Devank Jain, Uttar Pradesh (IN)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Jan. 19, 2021, as Appl. No. 17/152,289.
Int. Cl. G06F 30/327 (2020.01); G06F 30/31 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/31 (2020.01)] 5 Claims
OG exemplary drawing
 
1. A computer-implemented method of checker completeness analysis comprising:
with a computer processor, measuring checker coverage following completion of a structural or functional formal verification analysis of a circuit design;
with the computer processor, performing register transfer level (RTL) based analysis of holes in the checker coverage to determine a list of interest signals on which one or more checkers can be written to reduce holes in the checker coverage;
with the computer processor, ranking each signal in the list of interest signals in an order determined by its respective probable impact on the reduction in holes in the checker coverage; and
reporting, via a graphical user interface, the ranked list of interest signals.