US 11,941,299 B2
MRAM access coordination systems and methods via pipeline in parallel
Benjamin Louie, Fremont, CA (US); Neal Berger, Cupertino, CA (US); and Lester Crudele, Tomball, TX (US)
Assigned to Integrated Silicon Solution, (Cayman) Inc., Grand Cayman (KY)
Filed by Integrated Silicon Solution, (Cayman) Inc., Grand Cayman (KY)
Filed on May 16, 2022, as Appl. No. 17/745,839.
Application 17/745,839 is a continuation of application No. 16/442,345, filed on Jun. 14, 2019, granted, now 11,334,288.
Application 16/442,345 is a continuation in part of application No. 16/275,088, filed on Feb. 13, 2019, granted, now 10,818,331, issued on Oct. 27, 2020.
Application 16/275,088 is a continuation in part of application No. 16/118,137, filed on Aug. 30, 2018, granted, now 10,546,625, issued on Jan. 28, 2020.
Application 16/118,137 is a continuation in part of application No. 15/855,855, filed on Dec. 27, 2017, granted, now 10,192,602, issued on Jan. 29, 2019.
Application 15/855,855 is a continuation in part of application No. 15/277,799, filed on Sep. 27, 2016, granted, now 10,366,774, issued on Jul. 30, 2019.
Claims priority of provisional application 62/691,506, filed on Jun. 28, 2018.
Claims priority of provisional application 62/685,218, filed on Jun. 14, 2018.
Prior Publication US 2022/0276807 A1, Sep. 1, 2022
Int. Cl. G06F 3/06 (2006.01); G11C 11/16 (2006.01); G11C 29/00 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0644 (2013.01); G06F 3/0673 (2013.01); G11C 11/1659 (2013.01); G11C 11/1693 (2013.01); G11C 29/846 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1677 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A memory device configured to store information for a processor, the processor accessing the memory device via a memory controller, comprising:
an array of addressable memory cells, wherein said addressable memory cells of said array comprise magnetic random access memory (MRAM) cells and wherein further said array is organized into a plurality of memory banks, and wherein the memory controller is configured to operate in accordance with requirements corresponding to a different type of memory than said addressable memory cells comprising magnetic random access memory (MRAM) cells;
an engine configured to control access to said addressable memory cells organized into said plurality of banks; and
a plurality of pipelines configured to perform access control and communication operations between said engine and said plurality of memory banks of said array of addressable memory cells, wherein at least a portion of operations associated with accessing a first memory bank of said plurality of memory banks via a first pipeline of said plurality of pipelines are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing a second memory bank of said plurality of memory banks via a second pipeline of said plurality of pipelines, wherein said operations associated with accessing the first and second memory banks of said plurality of memory banks are coordinated to compensate for differences in operational requirements of the memory controller and operational constraints of said array of addressable memory cells.