CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G11C 7/1066 (2013.01); G11C 8/18 (2013.01)] | 16 Claims |
1. A memory system comprising:
a host circuit configured to control a bandwidth of a command-address signal based on data driving cycle information and transfer, to a memory circuit, the command-address signal with the bandwidth; and
the memory circuit configured to perform an input/output operation of a data signal based on the command-address signal and the data driving cycle information.
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