US 11,941,292 B2
Memory system and operating method thereof
Jae Hoon Kim, Icheon (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Oct. 4, 2021, as Appl. No. 17/493,657.
Claims priority of application No. 10-2021-0065345 (KR), filed on May 21, 2021.
Prior Publication US 2022/0374170 A1, Nov. 24, 2022
Int. Cl. G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 8/18 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G11C 7/1066 (2013.01); G11C 8/18 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory system comprising:
a host circuit configured to control a bandwidth of a command-address signal based on data driving cycle information and transfer, to a memory circuit, the command-address signal with the bandwidth; and
the memory circuit configured to perform an input/output operation of a data signal based on the command-address signal and the data driving cycle information.