US 11,941,291 B2
Memory sub-system command fencing
Dhawal Bavishi, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 2, 2021, as Appl. No. 17/464,813.
Prior Publication US 2023/0068061 A1, Mar. 2, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a first number of commands for execution on a memory sub-system;
receiving a second number of commands for execution on the memory sub-system;
receiving a memory fencing command associated with the first number of commands and the second number of commands, wherein a latency associated with executing the first number of commands is greater than a latency associated with executing the second number of commands; and
executing at least one of the first number of commands before executing at least one of the second number of commands in response to receiving the memory fencing command, wherein the memory fencing command prevents a non-deterministic protocol used by the memory sub-system from performing the second number of commands with lower latency before the first number of commands with higher latency, wherein the memory fencing command is configured to execute the first number of commands to move data from a first location to a second location in the memory sub-system before executing the second number of commands to read the data from the second location in the memory sub-system.