US 11,941,285 B2
Mitigating slow read disturb in a memory sub-system
Vamsi Pavan Rayaprolu, San Jose, CA (US); Kishore Kumar Muchherla, Fremont, CA (US); Ashutosh Malshe, Fremont, CA (US); Giuseppina Puzzilli, Boise, ID (US); and Saeed Sharifi Tehrani, San Diego, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 20, 2021, as Appl. No. 17/235,216.
Prior Publication US 2022/0334756 A1, Oct. 20, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receiving a read request to perform a read operation on a block of the memory device;
determining whether an entry corresponding to the block is stored in a data structure associated with the memory device;
responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device;
resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device;
determining that the counter and the timer satisfy a first criterion, wherein the first criterion corresponds to respective final values of the counter and the timer, and wherein satisfying the first criterion is indicative of a minimum number of read operations performed on the block; and
responsive to determining that the counter and the timer satisfy the first criterion, issuing a voltage discharge command to the block, wherein issuing the voltage discharge command results in the block reaching a ground voltage.