CPC G06F 3/065 (2013.01) [G06F 3/0616 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01)] | 16 Claims |
1. A system, comprising:
a memory device including an array of non-volatile memory cells, the memory device storing a first data set; and
a processor configured to perform the steps of:
detecting a trigger event that causes the processor to execute a memory update operation, and
executing the memory update operation by performing steps including:
creating a backup copy of the first data set,
storing the backup copy in the memory device, and
after storing the backup copy in the memory device, causing a memory controller to set a memory update flag stored in the memory device, wherein the memory update flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, wherein:
the memory controller is connected to the array of non-volatile memory cells and to the processor, the memory controller being configured to perform the steps of:
receiving a first instruction from the processor to set the memory update flag, and
setting the memory update flag by performing steps including:
programming the first memory cell to a first voltage value that exceeds a first threshold voltage of the first memory cell, and
after programming the first memory cell to the first voltage value, programming the second memory cell to a second voltage value that is less than a second threshold voltage of the second memory cell.
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