US 11,941,277 B2
Combination scan management for block families of a memory device
Shane Nowell, Boise, ID (US); Michael Sheperek, Longmont, CO (US); Larry J. Koudele, Erie, CO (US); and Vamsi Pavan Rayaprolu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Mar. 6, 2023, as Appl. No. 18/118,082.
Application 18/118,082 is a continuation of application No. 17/100,709, filed on Nov. 20, 2020, granted, now 11,625,177.
Prior Publication US 2023/0205442 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0629 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device is to perform operations comprising:
performing a read operation on a plurality of block families of the memory device; and
responsive to determining that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merging the first block family and the second block family, wherein the combining criterion is based on a data state metric reflecting a temporal voltage shift (TVS) of blocks associated with the first block family and the second block family.