US 11,941,276 B2
Incomplete superblock management for memory systems
Tomer Eliash, Sunnyvale, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 28, 2022, as Appl. No. 17/875,521.
Prior Publication US 2024/0036752 A1, Feb. 1, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0629 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a set of memory components of a memory sub-system; and
a processing device operatively coupled to the set of memory components, the processing device being configured to perform operations comprising:
grouping a plurality of sets of blocks of the set of memory components into respective ones of a plurality of superblocks;
determining that one or more blocks of an individual superblock of the plurality of superblocks are associated with a reliability grade that is lower than a threshold;
designating the individual superblock as an incomplete superblock; and
performing one or more memory operations on a portion of the plurality of superblocks comprising complete superblocks before the incomplete superblock.