CPC G06F 3/0619 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 13/1636 (2013.01); G06F 13/1689 (2013.01); G06Q 10/00 (2013.01); G06Q 20/00 (2013.01); G11C 7/02 (2013.01); G11C 11/406 (2013.01); G11C 11/40611 (2013.01); G11C 11/40615 (2013.01); G11C 11/40618 (2013.01); G11C 2211/4061 (2013.01)] | 20 Claims |
1. A memory device comprising a dynamic random access memory (DRAM) chip that includes:
a plurality of memory banks, each bank including a plurality of rows of memory cells;
a command interface operable to receive a refresh command from a memory controller external to the DRAM chip;
refresh circuitry configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller; and
control logic to configure the command interface to enter a calibration mode during the refresh time interval;
wherein the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.
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