US 11,941,254 B2
Test memory sub-systems through validation of responses to proof of space challenges
Joseph Harold Steinmetz, Loomis, CA (US); and Luca Bert, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 14, 2021, as Appl. No. 17/550,795.
Prior Publication US 2023/0185459 A1, Jun. 15, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
writing a proof of space plot into memory cells of a memory sub-system;
generating a plurality of random challenges of proof of space;
generating, using the proof of space plot stored in the memory cells, a plurality of responses to the plurality of random challenges respectively; and
determining validity of the plurality of responses.