US 11,941,251 B2
Nonvolatile memory including intermediate buffer and input/output buffer and memory system including the nonvolatile memory
Yoshihisa Kojima, Kawasaki (JP); Masanobu Shirakawa, Chigasaki (JP); and Kiyotaka Iwasaki, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Nov. 8, 2022, as Appl. No. 17/982,840.
Application 17/982,840 is a continuation of application No. 17/332,117, filed on May 27, 2021, granted, now 11,543,969.
Application 17/332,117 is a continuation of application No. 16/560,200, filed on Sep. 4, 2019, granted, now 11,068,167, issued on Jul. 20, 2021.
Claims priority of application No. 2018-174120 (JP), filed on Sep. 18, 2018.
Prior Publication US 2023/0056583 A1, Feb. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of controlling a nonvolatile memory, the nonvolatile memory including a memory cell array including a plurality of pages, an input/output buffer, and one or more intermediate buffers each electrically connected between the memory cell array and the input/output buffer, said method comprising:
storing, in a first intermediate buffer, data read through a sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a first sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers; and
storing, in the input/output buffer, data read through a sensing operation from a third page out of the plurality of pages in accordance with a third command that includes a third sensing operation instruction and does not include designation of any of the intermediate buffers, and outputting the data stored in the input/output buffer in accordance with a fourth command that includes an output instruction.