US 11,941,250 B2
Optimizing application execution based on memory-level parallelism (MLP)-based metrics
Sanyam Mehta, Bloomington, MN (US)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, Houston, TX (US)
Filed on May 6, 2022, as Appl. No. 17/662,356.
Prior Publication US 2023/0359358 A1, Nov. 9, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/0811 (2016.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0673 (2013.01); G06F 12/0811 (2013.01); G06F 2212/604 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a hardware processor; and
a memory to store instructions that, when executed by the hardware processor cause the hardware processor to:
determine a memory bandwidth of a processor subsystem corresponding to an execution of an application by the processor subsystem;
determine an average memory latency corresponding to the execution of the application by the processor subsystem;
determine a metric characterizing a memory level-parallelism associated with the execution of the application by the processor subsystem based on the memory bandwidth and the average memory latency; and
based on the metric, generate data representing a recommendation of an optimization to be applied to the application.