CPC G06F 3/0611 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0673 (2013.01); G06F 12/0811 (2013.01); G06F 2212/604 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a hardware processor; and
a memory to store instructions that, when executed by the hardware processor cause the hardware processor to:
determine a memory bandwidth of a processor subsystem corresponding to an execution of an application by the processor subsystem;
determine an average memory latency corresponding to the execution of the application by the processor subsystem;
determine a metric characterizing a memory level-parallelism associated with the execution of the application by the processor subsystem based on the memory bandwidth and the average memory latency; and
based on the metric, generate data representing a recommendation of an optimization to be applied to the application.
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