US 11,940,948 B2
Electronic device having multiple processing units and multiple memory units, and processing method thereof
Jingang Peng, Beijing (CN)
Assigned to LENOVO (BEIJING) LIMITED, Beijing (CN)
Filed by Lenovo (Beijing) Limited, Beijing (CN)
Filed on Mar. 7, 2022, as Appl. No. 17/688,515.
Claims priority of application No. 202111163102.1 (CN), filed on Sep. 30, 2021.
Prior Publication US 2023/0093805 A1, Mar. 30, 2023
Int. Cl. G06F 15/80 (2006.01); G06F 3/06 (2006.01); G06T 1/20 (2006.01)
CPC G06F 15/8061 (2013.01) [G06F 3/0653 (2013.01); G06T 1/20 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a first processing unit and a second processing unit;
a first memory unit correspondingly set for the first processing unit and configured for data access by the first processing unit, the first memory unit including a first main memory and a second main memory;
a second memory unit correspondingly set for the second processing unit and configured for data access by the second processing unit;
a first memory controller; and
a second memory controller,
wherein:
the first processing unit is configured to:
when accessing data in the first memory unit, access data in the first main memory through the first memory controller and/or access data in the second main memory through the second memory controller; and
occupy at least part of storage space of the second memory unit when a first criteria is met; and/or
the second processing unit is configured to occupy at least part of storage space of the first memory unit when a second criteria is met, including accessing data in the second main memory through the second memory controller when a load condition is met.