US 11,940,947 B2
Hardware accelerated anomaly detection using a min/max collector in a system on a chip
Ching-Yu Hung, Pleasanton, CA (US); Ravi P. Singh, Austin, TX (US); Jagadeesh Sankaran, Dublin, CA (US); Yen-Te Shih, Zhubei (TW); and Ahmad Itani, San Jose, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Jan. 6, 2023, as Appl. No. 18/151,009.
Application 18/151,009 is a continuation of application No. 17/391,425, filed on Aug. 2, 2021, granted, now 11,636,063.
Prior Publication US 2023/0153266 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/80 (2006.01); G06F 15/78 (2006.01); G06N 3/063 (2023.01); G06N 3/10 (2006.01)
CPC G06F 15/8053 (2013.01) [G06F 15/7807 (2013.01); G06F 15/8007 (2013.01); G06N 3/063 (2013.01); G06N 3/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
updating, based at least on one or more values computed using one or more processing units, at least one of a currently stored minimum value of a hardware unit to include a first value of the one or more values or a currently stored maximum value of the hardware unit to include a second value of the one or more values; and
determining whether at least one of the currently stored minimum value of the hardware unit or the currently stored maximum value of the hardware unit satisfies one or more threshold values.