US 11,940,945 B2
Reconfigurable SIMD engine
Heonchul Park, Pleasanton, CA (US)
Filed by CEREMORPHIC, INC., San Jose, CA (US)
Filed on Dec. 31, 2021, as Appl. No. 17/566,848.
Prior Publication US 2023/0214351 A1, Jul. 6, 2023
Int. Cl. G06F 15/00 (2006.01); G06F 9/38 (2018.01); G06F 15/80 (2006.01); G06F 15/78 (2006.01)
CPC G06F 15/8007 (2013.01) [G06F 9/382 (2013.01); G06F 15/7889 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an instruction memory storing a sequence of executable instructions, the executable instructions comprising a mixture of single instruction multiple data (SIMD) executable instructions containing multiple operands, and executable instructions containing single operands;
a fetch stage retrieving an executable instruction from the instruction memory;
a decode stage configured to receive the executable instruction from the fetch stage, the decode stage identifying and separating data operands;
the decode stage coupled to an output of the fetch stage and transmitting the executable instructions containing the single operand to an execution stage for processing and transmitting the executable instructions containing multiple operands to at least one SIMD processing element (SPE) for processing, the decode stage also providing control signals associated with the executable instructions containing multiple operands to a control memory;
the at least one SPE operably coupled to the control memory to receive from the control memory at least one SPE control signal stored by the control memory, wherein the at least one SPE is configured to perform a selected operation on a portion of a data word, and wherein the selected operation is determined as a function of the at least one SPE control signal read from the control memory.