US 11,940,928 B2
Parking threads in barrel processor for managing cache eviction requests
Christopher Baronne, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 29, 2022, as Appl. No. 17/897,913.
Prior Publication US 2024/0070088 A1, Feb. 29, 2024
Int. Cl. G06F 12/126 (2016.01)
CPC G06F 12/126 (2013.01) [G06F 2212/1044 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a barrel processor, comprising:
eviction circuitry;
wherein the barrel processor is configured to perform operations using the eviction circuitry to:
(a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor;
(b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation;
(c) copy the thread into a park queue;
(d) evict a data cache line from the data cache;
(e) identify an empty cycle in the memory request pipeline;
(f) schedule the thread to execute during the empty cycle; and
(g) remove the thread from the park queue.