US 11,940,926 B2
Creating high density logical to physical mapping
Stephen Hanna, Fort Collins, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 13, 2022, as Appl. No. 17/663,255.
Prior Publication US 2023/0367718 A1, Nov. 16, 2023
Int. Cl. G06F 12/1009 (2016.01); G06F 12/02 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive a command associated with data having a corresponding set of logical addresses;
determine whether a subset of logical addresses of the set of logical addresses is sequential;
generate a set of entries based at least in part on the determining, each entry of the set of entries indicating a mapping between a logical address of the set of logical addresses and a physical address of a set of physical addresses, the set of entries associated with a first level of a mapping information; and
store a coalesced entry comprising the subset of logical addresses in a second level of the mapping information based at least in part on the generating, the entry indicating the mapping between the set of logical addresses and the set of physical addresses based at least in part on the subset of logical addresses being sequential.