US 11,940,922 B2
ISA extension for high-bandwidth memory
Mu-Tien Chang, Santa Clara, CA (US); Krishna T. Malladi, San Jose, CA (US); Dimin Niu, Sunnyvale, CA (US); and Hongzhong Zheng, Los Gatos, CA (US)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 14, 2022, as Appl. No. 18/081,488.
Application 18/081,488 is a continuation of application No. 17/121,488, filed on Dec. 14, 2020, granted, now 11,556,476.
Application 17/121,488 is a continuation of application No. 15/854,557, filed on Dec. 26, 2017, granted, now 10,866,900, issued on Dec. 15, 2020.
Claims priority of provisional application 62/573,390, filed on Oct. 17, 2017.
Prior Publication US 2023/0119291 A1, Apr. 20, 2023
Int. Cl. G06F 12/0875 (2016.01); G06F 13/12 (2006.01); G06F 13/16 (2006.01); G06F 9/30 (2018.01)
CPC G06F 12/0875 (2013.01) [G06F 13/124 (2013.01); G06F 13/1636 (2013.01); G06F 13/1689 (2013.01); G06F 9/3001 (2013.01); G06F 9/30098 (2013.01); G06F 2212/452 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A method of processing in-memory commands in a high-bandwidth memory (HBM) system, the method comprising:
sending, by an HBM memory controller of a processor, a function-in-HBM (FIM) instruction to an HBM, wherein the FIM instruction comprises an atomic operation generated by the processor by merging a first instruction of a first type and a second instruction of a second type into an atomic instruction;
receiving the FIM instruction at a logic component of the HBM, wherein the logic component comprises: a controller, an Arithmetic Logic Unit (ALU), and a SRAM configured as a scratchpad; and
coordinating execution of the atomic operation of the FIM instruction, by the logic component using the controller and at least one of a DRAM, the ALU, or the SRAM.