US 11,940,921 B2
Bounding box prefetcher
Douglas Raye Reed, Austin, TX (US)
Assigned to CENTAUR TECHNOLOGY, INC., Austin, TX (US)
Filed by CENTAUR TECHNOLOGY, INC., Austin, TX (US)
Filed on Jan. 7, 2022, as Appl. No. 17/570,452.
Prior Publication US 2023/0222064 A1, Jul. 13, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 12/0811 (2013.01); G06F 2212/602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microprocessor, comprising:
an L1 cache;
an L2 cache comprising a bounding box prefetch unit and an L2 fill queue, the bounding box prefetch unit configured to allocate an entry in the L2 fill queue based on a miss in the L2 cache; and
an L3 cache;
wherein, based on the allocation, the bounding box prefetch unit is configured to:
issue all prefetches remaining for a memory block as L3 prefetches based on a set of conditions; and
issue L2 prefetches for plural cache lines corresponding to the L3 prefetches upon the plural cache lines obtained from the L3 prefetches reaching an end of the memory block.