| CPC G06F 12/0855 (2013.01) [G06F 12/0891 (2013.01)] | 24 Claims |
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1. An apparatus comprising:
a cache including a cache line;
an interface to an external entity; and
processing circuitry configured to:
maintain a queue for the cache line, the queue including a deferred memory request to operate on a memory address currently associated with the cache line, metadata for the queue being stored in a tag of the cache line;
determine that a recall is needed to process the deferred memory request, the recall being a change of control of the cache line from the external entity;
write, in response to the determination that the recall is needed, the metadata of the queue from the tag to a first recall storage corresponding to the cache line, the first recall storage referenced by a memory request ID corresponding to the deferred memory request;
transmit, via the interface, a recall request including a message ID to the external entity;
write, in response to transmission of the recall request, the memory request ID to a second recall storage referenced by the message ID; and
restore the queue for the cache line, based on a response to the recall request and an eviction of the cache line, from the first recall storage, the response including the message ID, the message ID used to retrieve the memory request ID from the second recall storage, and the memory request ID used to reference the first recall storage.
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