US 11,940,909 B2
Dynamic mapping of data to lower latency memory based on data access
Sriramakrishan Govindarajan, Bengaluru (IN); Mihir Narendra Mody, Bengaluru (IN); and Prithvi Shankar Yeyyadi Anantha, Bengaluru (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 26, 2022, as Appl. No. 17/729,252.
Prior Publication US 2023/0342292 A1, Oct. 26, 2023
Int. Cl. G06F 12/02 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 2212/7201 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a transaction tracker configured to:
maintain a location mapping for each of a plurality of memory blocks, wherein each of the location mapping references at least one of a first memory and a second memory,
wherein the first memory is configured to store a copy of each memory block of the plurality of memory blocks stored at the second memory for which an access frequency of the memory block satisfies an access threshold for the memory block, in which the access frequency of the memory block is weighted more heavily for access requests of the memory block within a subset of a time in which access requests for the first memory block have been made; and
a transaction mapper configured to:
receive a request from a processor core for access to a first memory block of the plurality of memory blocks,
obtain, from the transaction tracker, a mapped address for the first memory block, and
remap the request to the mapped address.