US 11,940,874 B2
Queue management for a memory system
Nitul Gohain, Bangalore (IN); Jonathan S. Parry, Boise, ID (US); and Reshmi Basu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 8, 2022, as Appl. No. 17/883,051.
Prior Publication US 2024/0045762 A1, Feb. 8, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/0772 (2013.01)] 25 Claims
OG exemplary drawing
 
25. A method, comprising:
receiving, at a memory system, a first command comprising first data, wherein the memory system comprises a first decoder associated with a first error control capability and a second decoder associated with a second error control capability;
determining whether to assign the first command to a first queue associated with the first decoder or a second queue associated with the second decoder based at least in part on an expected latency for performing an error control operation on the first data using the first decoder; and
processing, by the first decoder, the first command according to the first error control capability based at least in part on assigning the first command to the first queue.