US 11,940,872 B2
Error correction code validation
Shaun Stephen Bradley, Patrickswell (IE); Bernard Sherwin Leung Chiw, Quezon (PH); Andreas G Callanan, Murroe (IE); Thomas J. Meany, Bruff (IE); and Pat Crowe, Doon (IE)
Assigned to Analog Devices International Unlimited Company, Limerick (IE)
Filed by Analog Devices International Unlimited Company, Limerick (IE)
Filed on Apr. 21, 2022, as Appl. No. 17/726,123.
Prior Publication US 2023/0342242 A1, Oct. 26, 2023
Int. Cl. H03M 13/00 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/1044 (2013.01) [G06F 11/1068 (2013.01); G11C 29/52 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array including memory cells to store memory data;
error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data; and
an ECC circuitry checker configured to:
translate a memory address of a memory operation to a memory address mapped portion of the memory array as part of an ECC checking operation;
retrieve check ECC data from the memory address mapped portion of the memory array according to the translated memory address, wherein the check ECC data is used to detect errors in the ECC circuitry;
substitute the ECC data with the check ECC data from the memory address mapped portion of the memory array to check the functioning of the ECC circuitry;
compare an output of the ECC circuitry to an expected ECC circuitry output when the substituted check ECC data is applied to the ECC circuitry; and
generate an alert when the comparing indicates an error in the ECC circuitry of the memory device.