US 11,940,871 B2
Memory system and memory control method
Yuki Mandai, Tokyo (JP); Shuou Nomura, Yokohama Kanagawa (JP); Ryo Yamaki, Yokohama Kanagawa (JP); and Toshikatsu Hida, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 25, 2022, as Appl. No. 17/895,465.
Claims priority of application No. 2022-019335 (JP), filed on Feb. 10, 2022.
Prior Publication US 2023/0251928 A1, Aug. 10, 2023
Int. Cl. G06F 11/10 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01)
CPC G06F 11/1024 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
11. A method for controlling a memory system having a nonvolatile memory including a plurality of memory cells, the method comprising:
reading first data through application of a first read voltage to each of the memory cells;
performing a first decoding process with respect to the first data;
when the first decoding process fails, performing a tracking process by:
reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, the second read voltages being shifted by a predetermined amount; and
obtaining, with respect to each of the memory cells, likelihood information indicating a likelihood that the memory cell in the second threshold voltage level represents a bit value of 0 or 1 using the second data; and
performing a second decoding process with respect to the second data using the likelihood information.