US 11,940,857 B2
Multi-element memory device with power control for individual elements
Deborah Lindsey Dressler, Newark, CA (US); Julia Kelly Cline, San Francisco, CA (US); and Wayne Frederick Ellis, Jericho Center, VT (US)
Assigned to RAMBUS INC., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Dec. 19, 2022, as Appl. No. 18/068,437.
Application 18/068,437 is a continuation of application No. 16/915,934, filed on Jun. 29, 2020, granted, now 11,531,386.
Application 16/915,934 is a continuation of application No. 15/972,018, filed on May 4, 2018, granted, now 10,698,464, issued on Jun. 30, 2020.
Application 15/972,018 is a continuation of application No. 15/017,395, filed on Feb. 5, 2016, granted, now 9,965,012, issued on May 8, 2018.
Application 15/017,395 is a continuation of application No. 14/127,886, granted, now 9,256,279, issued on Feb. 9, 2016, previously published as PCT/US2012/042075, filed on Jun. 12, 2012.
Claims priority of provisional application 61/502,495, filed on Jun. 29, 2011.
Prior Publication US 2023/0297151 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/28 (2006.01); G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 13/42 (2006.01); G11C 5/06 (2006.01)
CPC G06F 1/28 (2013.01) [G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 13/4273 (2013.01); G11C 5/063 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A host device for controlling operation of a multi-element device having a plurality of memory elements, wherein a respective memory element of the plurality of memory elements includes:
a memory array;
access circuitry, to control access to the memory array;
power control circuitry, including one or more control registers storing a first control value, the power control circuitry to control distribution of power to the access circuitry in accordance with the first control value stored in the one or more control registers; and
sideband circuitry for enabling the host device to set at least the first control value in the one or more control registers;
the host device comprising:
control circuitry configured to set the first control value in the one or more control registers of the respective memory element of the plurality of memory elements;
wherein:
the first control value, stored in the one or more control registers, is received from the host device and controls distribution of power to access circuitry of the respective memory element, which controls access to the memory array of the respective memory element, without controlling distribution of power to the memory array of the respective memory element;
the host device is external to the multi-element device;
the control circuitry is configured to send the first control value via the sideband circuitry of the respective memory element for storage in the one or more control registers.